1. Field of the Invention
The present invention relates to low dropout regulators, and particularly, to an integrated LDO with a variable resistive load compensation scheme.
2. Description of the Prior Art
Voltage regulator circuits are circuits placed between a power supply and a load circuit for providing a constant voltage to the load circuit regardless of fluctuations in power supply voltage. For example, a battery used to power a mobile phone may have a decreasing output voltage as the battery loses charge. In this case, the voltage regulator circuit can supply the constant voltage to the load circuit as long as the output voltage of the battery is greater than the constant voltage supplied to the load circuit of the mobile phone. A dropout voltage is then defined as a minimum voltage difference that must be present from an input of the voltage regulator to an output of the voltage regulator for the voltage regulator to supply the constant voltage. For example, a voltage regulator that supplies a constant voltage of 1.8V may be able to supply 1.8V as long as a power supply voltage is above 2.0V, in which case the dropout voltage is 200 mV (2.0V−1.8V). Low dropout regulators (LDOs) are voltage regulators that have a low dropout voltage. In modern applications, LDOs with dropout voltages lower than 50 mV are available.
Please refer to FIG. 1, which is a diagram of an LDO regulator 10 with a first compensation scheme. The LDO regulator 10 comprises a first stage amplifier 101, an inverting amplifier 102, a pass transistor MP, a mirror transistor MS, a current-to-voltage (I-V) convertor 103, a compensation capacitor CC, and a compensation resistor RC. The LDO regulator 10 outputs an output voltage OUT that is nominally constant for all input voltages VDD. A load ZL draws a load current IL from VDD through the pass transistor MP. A first resistor RA and a second resistor RB generates a voltage proportional to OUT that is compared with the reference voltage VREF to control OUT via the amplifiers 101, 102 and the pass transistor MP. The compensation capacitor CC and the compensation resistor RC provide frequency compensation that varies with the current outputted by the pass transistor MP due to voltage applied to the compensation resistor RC through the mirror transistor MS and the I-V convertor 103.
Please refer to FIG. 2, which is a diagram of an LDO regulator 20 with a second compensation scheme. The LDO regulator 20 comprises a first stage amplifier 201, a buffer 202, a pass transistor MP, a first resistor RA, a second resistor RB, a compensation resistor RC, and a compensation capacitor CC. The LDO regulator 20 outputs an output voltage OUT that is nominally constant for all input voltages VREF. A load ZL draws a current from the pass transistor MP. In operation, the LDO regulator 20 is similar to the LDO regulator 10. In addition, the first compensation scheme and the second compensation scheme vary slightly, but are similar in principle.
The LDO regulators 10, 20 described above have a number of drawbacks. First, the PSRR of both of the LDO regulators 10, 20 is not sufficiently high. This can be understood as follows. For the LDO regulator 10 in FIG. 1, a capacitance of value CL1=(1+A)CC loads the high impedance output terminal X of the first stage to AC ground. For the LDO regulator 20 in FIG. 2, a capacitance of value CL1=CC loads the high impedance output terminal X of the first stage to AC ground. It is to be noted that for adequate compensation, CC needs to be large for FIG. 2. Because of this, the PSRR frequency responses of the LDO regulators 10, 20 will each have a zero at 1/2πCL1ro1, where ro1 is the output resistance of the first stage.
Secondly, the compensations of the LDO regulators 10, 20 are not applied from the output node OUT. This means that the compensations do not move the output pole to a higher frequency.
Thirdly, the variable compensation resistors RC of the LDO regulators 10, 20 are MOSFETs. Therefore, in each case, tracking compensation provided by the variable compensation resistor RC is subject to substantial process variation and temperature variation of the MOSFET.